A memory overhead evaluation of the interleaved signature instruction stream

Using a watchdog processor for concurrent error detection of a processor execution flow is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor instruction stream creating noticeable memory and performance overheads. The interleaved signature instruction stream (ISIS) technique is a signature embedding technique that allows signatures to co-exist with the main instruction stream with a minimal impact on processor performance, without sacrificing error detection coverage or latency. This technique has been implemented into HORUS, a MIPS-like RISC processor developed in VHDL. This paper presents the HORUS architecture novelties demanded by ISIS, discusses the performance impact of adding an ISIS watchdog processor and provides results of ISIS memory overhead. These results are compared against similar solutions previously presented in the literature.