DocumentCode
3090792
Title
Fault-tolerant CAM architectures: a design framework
Author
Salice, F. ; Sami, M.G. ; Stefanelli, R.
Author_Institution
DEI, Politecnico di Milano, Italy
fYear
2002
fDate
2002
Firstpage
233
Lastpage
241
Abstract
Presents a novel design framework for designing fault tolerant/self-checking content addressable memories (CAM). The proposed methodology produces a CAM structural architecture starting from a functional description of some high level properties of the device (design directives). The analysis focuses on the functional level; in particular, the paper concentrates on functional level synthesis, by considering the transformation from the functional description to the structural definition. Some examples will be provided as support to the description.
Keywords
content-addressable storage; fault tolerant computing; high level synthesis; memory architecture; content addressable memories; design directives; design framework; fault-tolerant CAM architectures; functional description; functional level synthesis; high level properties; structural architecture; structural definition; CADCAM; Circuit faults; Computer aided manufacturing; Design methodology; Fault detection; Fault diagnosis; Fault tolerance; Flip-flops; Network synthesis; Pattern matching;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-1831-1
Type
conf
DOI
10.1109/DFTVS.2002.1173520
Filename
1173520
Link To Document