AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis

Reusing embedded resources for implementing built- in self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement cost- efficient built-in self test functions from the AES cryptoalgorithm hardware implementation in a secure system. Self-test of the proposed implementation is also presented. A statistical test suite and fault-simulation are used for evaluating the efficiency of the corresponding cryptocore as pseudo-random test pattern generator; an analytical approach demonstrates the low probability of aliasing when used for test response compaction.