DocumentCode
3090814
Title
Using run-time reconfiguration for fault injection in hardware prototypes
Author
Antoni, Lörinc ; Leveugle, Régis ; Fehér, Béla
Author_Institution
TIMA Lab., Grenoble, France
fYear
2002
fDate
2002
Firstpage
245
Lastpage
253
Abstract
In this paper, a new methodology for the injection of single event upsets (SEU) in memory elements is introduced. SEUs in memory elements can occur due to many reasons (e.g. particle hits, radiation) and at any time. It becomes therefore important to examine the behaviour of circuits when an SEU occurs in them. Reconfigurable hardware (especially FPGAs) was shown to be suitable to emulate the behaviour of a logic design and to realise fault injection. The proposed methodology for SEU injection exploits FPGAs and, contrarily to the most common fault injection techniques, realises the injection directly in the reconfigurable hardware, taking advantage of run-time reconfiguration capabilities of the device. In this case, no modification of the initial design description is needed to inject a fault, that results in avoiding hardware overheads and specific synthesis, place and route phases.
Keywords
VLSI; fault tolerance; field programmable gate arrays; hardware description languages; integrated circuit design; integrated memory circuits; network routing; radiation effects; reconfigurable architectures; SEU; design description; fault injection; hardware overheads; hardware prototypes; memory elements; particle hits; radiation; reconfigurable hardware; route phases; run-time reconfiguration; Circuit faults; Circuit synthesis; Circuit testing; Field programmable gate arrays; Hardware; Laboratories; Power system modeling; Prototypes; Runtime; Single event upset;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-1831-1
Type
conf
DOI
10.1109/DFTVS.2002.1173521
Filename
1173521
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