DocumentCode :
3090827
Title :
A Case Study on At-Speed Testing for a Gigahertz Microprocessor
Author :
Wang, Da ; Li, Rui ; Hu, Yu ; Li, Huawei ; Li, Xiaowei
Author_Institution :
Chinese Acad. of Sci., Beijing
fYear :
2008
fDate :
23-25 Jan. 2008
Firstpage :
326
Lastpage :
331
Abstract :
This paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertz microprocessor with multi-clock domains. The presented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compression structure to reduce test data volume. It is difficult and time-consuming to generate at-speed tests for a design with embedded memories and multi-clock domains. The proposed test pattern generation scheme can gain transition fault coverage of approximately 83% for this high-performance microprocessor, and the test power consumption is well controlled.
Keywords :
automatic test pattern generation; boundary scan testing; design for testability; microprocessor chips; at-speed testing; complex test clock sequences; design for testability method; embedded memories; gigahertz microprocessor; hybrid scan compression structure; internal phase-locked loops; multiclock domains; test data volume; test pattern generation scheme; transition fault coverage; Circuit faults; Circuit testing; Clocks; Costs; Electronic equipment testing; Energy consumption; Logic testing; Microprocessors; System testing; Test pattern generators; at-speed testing; test coverage; test data volume; test power consumption; test time;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on
Conference_Location :
Hong Kong
Print_ISBN :
978-0-7695-3110-6
Type :
conf
DOI :
10.1109/DELTA.2008.27
Filename :
4459565
Link To Document :
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