Fault list compaction through static timing analysis for efficient fault injection experiments

With the adoption of deep sub-micron technologies, faults modeled as single event transients (SETS) on combinational gates are becoming an issue, but efficient and accurate techniques for assessing their impact on VLSI designs are still missing. This paper presents a new approach for generating the list of faults to be addressed during fault injection experiments tackling SET effects. By resorting to static timing analysis, the approach is able to prune the set of possible faults and to identify a superset of the ones that may produce effects on the circuit outputs. Experimental results are reported on standard benchmarks assessing the effectiveness of the proposed approach.