DocumentCode
3090846
Title
A Charge Pump Circuit --- Cascading High-Voltage Clock Generator
Author
Huang, Wen Chang ; Cheng, Jin Chang ; Liou, Po Chih
Author_Institution
Kun Shan Univ., Tainan
fYear
2008
fDate
23-25 Jan. 2008
Firstpage
332
Lastpage
337
Abstract
A high efficiency charge pump circuit which is realized by multi-staged high-voltage clock (HVC) generator is presented. The ten-staged HVC charge pump circuit could pump the voltage up to 21.35 V at a supply voltage of 2 V in 0.35 mum CMOS process. It also shows that the clock voltage increased linearly as the stages of the high-voltage clock generator was increased. No saturation tendency of the pumping voltage was observed after the ten-stage of pumping.
Keywords
CMOS digital integrated circuits; clocks; CMOS process; charge pump circuit; multistaged high-voltage clock generator; size 0.35 mum; voltage 2 V; Charge pumps; Charge transfer; Circuit testing; Clocks; Electronic equipment testing; Nonvolatile memory; Switches; Switching circuits; System testing; Threshold voltage; Charge pump; voltage doubler;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on
Conference_Location
Hong Kong
Print_ISBN
978-0-7695-3110-6
Type
conf
DOI
10.1109/DELTA.2008.94
Filename
4459566
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