DocumentCode :
3090907
Title :
Testing layered interconnection networks
Author :
Lombardi, F. ; Park, N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
fYear :
2002
fDate :
2002
Firstpage :
293
Lastpage :
301
Abstract :
This paper presents an approach for fault detection in layered interconnection networks (LINs). A LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires to configure the LIN multiple times. Using a graph approach, it is proved that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results inn the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow, such that the maximal degree can be iteratively decreased, while guaranteeing the existence of art appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 % fault coverage of bridge faults a post-processing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N4W L), where N is the total number of nets, W is the number of switches per switching element and L is the number of layers. Extensive simulation results are provided.
Keywords :
automatic testing; computational complexity; fault diagnosis; graph theory; integrated circuit testing; logic testing; multistage interconnection networks; bridge faults; complexity bounds; execution complexity; fault coverage; fault detection; fault model; generalized multistage interconnection network; graph approach; layered interconnection network testing; net adjacencies; network flow algorithm; node disjoint path sets; post-processing algorithm; test vector generation; Bridges; Communication switching; Computational modeling; Fault detection; Fault tolerance; Iterative algorithms; Multiprocessor interconnection networks; Routing; Switches; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
ISSN :
1550-5774
Print_ISBN :
0-7695-1831-1
Type :
conf
DOI :
10.1109/DFTVS.2002.1173526
Filename :
1173526
Link To Document :
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