Title :
Yield modeling of a WSI telecom router architecture
Author :
Qiu, Bing ; Savaria, Yvon ; Lu, Meng ; Wang, Chunyan ; Thibeault, Claude
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
This paper presents a closed form yield model that takes into account the constraints of an architecture. It applies to architectures that approximate global redundancy and for which the constraints translate into yield losses. The impact of the constraints on yield was evaluated by calculating the probability of observing non-tolerable defect patterns and by subtracting these probabilities from the yield of arrays with global redundancy. It is shown that most of the yield losses come from a few patterns comprising a small number of defects. A relatively sharp threshold in the yield to defect density relationship is observed. This paper also proposes a regression yield model. Using a simple regression analysis, a simplified model accurately predicts the slope and pivot point of true yield curves. These models can be used to predict when more redundancy is needed for given array and cells sizes.
Keywords :
cellular arrays; integrated circuit modelling; integrated circuit yield; redundancy; statistical analysis; telecommunication network routing; wafer-scale integration; WSI telecom router architecture; closed form yield model; global redundancy; nontolerable defect patterns; probability; regression analysis; regression yield model; yield curves; yield losses; yield to defect density relationship; Electronic mail; Integrated circuit interconnections; Integrated circuit yield; Logic arrays; Predictive models; Probability; Reconfigurable logic; Regression analysis; Robustness; Telecommunications;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
Print_ISBN :
0-7695-1831-1
DOI :
10.1109/DFTVS.2002.1173528