Feasibility study of designing TSC sequential circuits with 100% fault coverage

Author

Piestrak, Stanislaw J.

Author_Institution

Inst. of Eng. Cybern., Wroclaw Univ. of Technol., Poland

fYear

2002

fDate

2002

Firstpage

354

Lastpage

362

Abstract

Several design methods of self-checking synchronous sequential circuits (SMs) have been proposed in the literature. Two principal drawbacks of all these methods are: 1) the internal fault coverage rarely equals to 100% and 2) the checkers used to monitor correct operation of a SM (claimed to be self-testing) contain internal faults which cannot be detected during normal operation by a subset of codewords which, are actually used. In this paper, we analyze the possibility of designing totally self-checking (TSC) SMs protected against errors using unordered codes with 100% fault coverage.

Keywords

VLSI; error detection codes; fault diagnosis; integrated circuit testing; logic CAD; sequential circuits; sequential machines; TSC sequential circuits; VLSI; codewords; fault coverage; internal fault coverage; internal faults; physical failures; self-checking circuits; unordered codes; Built-in self-test; Circuit faults; Design methodology; Electrical fault detection; Encoding; Fault detection; Protection; Samarium; Sequential circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-1831-1

Type

conf

DOI

10.1109/DFTVS.2002.1173532

Filename

1173532