Title :
CMOS standard cells characterization for IDDQ testing
Author :
Pleskacz, Witold A. ; Borejko, Tomasz ; Kuzmicz, Wieslaw
Author_Institution :
Inst. of Microelectron. & Optoelectronics, Warsaw Univ. of Technol., Warszawa, Poland
Abstract :
This paper describes the CMOS standard cells characterization methodology for IDDQ testing. Defect statistics were taken into account and critical area approach was used to generate compact test sets. The proposed methodology allows one to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. Experimental results for gates from an industrial standard cell library were presented. The complete bridging fault set and different types of the simulation conditions of shorts at inputs of logic gates ("Wired-AND" and "Wired-OR" conditions) were considered.
Keywords :
CMOS logic circuits; VLSI; cellular arrays; circuit simulation; fault simulation; integrated circuit testing; logic testing; CMOS standard cells; IDDQ testing; bridging fault set; characterization methodology; compact test sets; critical area approach; industrial standard cell library; input test vectors; probabilities; simulation conditions; wired-AND conditions; wired-OR conditions; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit testing; Libraries; Pollution measurement; Power supplies; Probability; Test pattern generators;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
Print_ISBN :
0-7695-1831-1
DOI :
10.1109/DFTVS.2002.1173536
