Title :
Low power techniques for flash memories
Author :
Canegallo, Roberto ; Dozza, Davide ; Guerrieri, Roberto
Author_Institution :
Innovative Syst. Design Group, STMicroelectron., Milan, Italy
Abstract :
Low power digital techniques to reduce power dissipation during write operations are implemented in 3V-only, 1M cells, NOR-flash memory. The test chip is fabricated in 0.5 μm, 3-metal, triple-cell CMOS technology. Measurement results show that these methods combined with conventional low current programming algorithms allow a reduction in power consumption of 40% with a 20% reduction of overhead in total chip area
Keywords :
CMOS memory circuits; NOR circuits; flash memories; integrated circuit design; low-power electronics; 0.5 micron; 3 V; NOR-flash memory; low current programming algorithms; low power techniques; power consumption; power dissipation; total chip area; triple-cell CMOS technology; write operations; Batteries; CMOS technology; Decoding; Energy consumption; Flash memory; Nonvolatile memory; Parasitic capacitance; Power dissipation; Testing; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922282
