Title :
Development of a low-power SRAM compiler
Author :
Jagasivamani, Meenatchi ; Ha, Dong Sam
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
With the proliferation of portable consumer electronics, power-consumption becomes a key design criterion, while the speed of memories is still the bottleneck for high-speed applications. In this paper, we discuss the development of an SRAM compiler with the capability to choose between a low-power and a high-speed SRAM. Experimental results show that the low-power version of our 1-kB SRAM can function at a minimum operating voltage of 2.1 V and dissipates 17.4 mW of average power at 20 MHz
Keywords :
SRAM chips; consumer electronics; high-speed integrated circuits; integrated circuit design; low-power electronics; 1 kB; 17.4 mW; 2.1 V; 20 MHz; average power; design criterion; high-speed SRAM; high-speed applications; low-power SRAM compiler; minimum operating voltage; portable consumer electronics; Application software; Capacitance; Circuit simulation; Consumer electronics; Decoding; Portable computers; Power dissipation; Random access memory; Telecommunication computing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922283
