Repairability evaluation of embedded multiple region DRAMs

This paper presents a method to evaluate the repairability of embedded redundant DRAMS with multiple regions. An architecture-oriented repairability evaluation method is proposed. This identifies the bounds on the repairability that provides the best and worst case repair success rate of a redundant DRAM architecture partitioned into multiple regions. A comparative study is conducted by using the proposed method to evaluate the repairabilities of different architectures. The novelty is that the proposed method can be driven without suffering from the NP-completeness of conventional repairability evaluation methods that rely on exhaustive and exponential search due to their being algorithm-oriented unless a heuristic is provided at a high cost of overhead. The repairability bounds of symmetric single subregion, multiple subregion DRAMS are investigated as criteria since the complexity of their repair algorithms drives algorithm-oriented repairability analysis methods impractical. Ultimately, the proposed method will establish a practical and cost-effective approach to assuring the yield and repairability of ultra high density embedded DRAM cores on System-on-Chip.