Modeling and Simulation Techniques for Voltage Drop Due to Multiple Input Switching Transitions

As IC technology scales down, the metal width is decreasing, making the resistance along the power lines increase substantially. Together with the nonlinear scaling of the threshold voltage that makes the ratio of the threshold voltage to the supply voltage rise, the IR drop becomes a serious problem in modern VLSI design. Thus, the verification of the power distribution network is of critical importance to ensure reliable performance. However, with the increasing number of transistors on a chip, the complexity of the power network has grown. The available computational power and memory resources impose limitations on the size of the networks that can be analyzed using currently known techniques. In this paper, we present a fast and efficient method to analyze power distribution networks in the time-domain. The key concepts in our approach are a current source-based model and a voltage controlled resistor. The library elements are pre-characterized with respect to the modeling requirements and their models are used during the transient simulation. The new model takes into account the multiple input switching (MIS) transitions including single input switching (SIS) transitions, which mostly neglected in the past due to the fact that the resulting current waveforms are difficult to model. The proposed techniques provide good analysis results compared to the reference with a reduction of the run-time by a factor of 200, although the cell pre-characterization is based on SPICE simulation. Our model is independent of power network parasitics, which implies that different power network scenarios may be analyzed based on the same model and the same cell characterizations. The run-time and accuracy of the proposed approach are demonstrated on some industrial designs.