Title :
A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process
Author :
Kim, JinKyung ; Jung, Sung-Kyu ; Jung, Ji-Hoon ; Sung, Sang-Kyung ; Lee, Kang-Yoon ; Nam, Chul ; Park, Bong-Hyuk ; Choi, Sang-Sung
Abstract :
This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra- Wideband) application using 0.13 um CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and prescaler architecture are also presented in this paper. A new coarse tuning scheme that utilizes the MIM capacitance and the varactor is proposed to expand the VCO tuning range. The single PLL and two SSB-mixers consume 75 mW from a 1.5 V supply. The VCO tuning range is 500 MHz. The simulated phase noise of the VCO is -110 dBc/Hz at 1 MHz offset. The die area is 3 times 2 mm2.
Keywords :
CMOS integrated circuits; MMIC mixers; OFDM modulation; frequency synthesizers; phase locked loops; prescalers; tuning; ultra wideband communication; varactors; voltage-controlled oscillators; MIM capacitance; RF CMOS process; frequency 3 GHz to 5 GHz; frequency 500 MHz; frequency planning; frequency synthesizers; multiband OFDM; power 75 mW; prescalers; size 0.13 mum; ultra wideband communication; voltage 1.5 V; voltage-controlled oscillators; CMOS process; Capacitance; Energy consumption; Frequency synthesizers; OFDM; Radio frequency; Tuning; Ultra wideband technology; Varactors; Voltage-controlled oscillators; Frequency Synthesizer; UWB; phase-locked loop (PLL); single-sideband (SSB) mixer;
Conference_Titel :
Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on
Conference_Location :
Hong Kong
Print_ISBN :
978-0-7695-3110-6
DOI :
10.1109/DELTA.2008.128