Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec

The issue of VLSI design of low latency/low power finite field multipliers is addressed and methods from logic structure, circuit design and physical mapping aspects are presented. With proposed architecture and physical mapping, an irregular balanced-tree parallel multiplier con be implemented as easy as a regular multiplier. The custom VLSI implementations of these multipliers over GF(2^m) show that the irregular multiplier has 53% smaller delay and 58% less power consumption than a regular multiplier