Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs

This paper presents a Vector DMA Cache (VDC)scheme between the DMA bus and the Vector Memory (VM) in vector DSPs. The VDC can effectively reduce the VM access counts from the DMA requests and decrease the VM access conflicts. The VDC is specially designed for the DMA and not for the CPU, so it has some unique techniques which differ from the traditional CPU cache scheme. The main techniques of the VDC include the separate read cache and write cache, full line auto-updating policy and software cache coherence. Experimental results show the single-port VM plus the VDC can make programs reach more than 95% execution efficiency with only 44.1% and 51.4% chip area and power cost, compared with the dual-port VM scheme. And the single-port VM plus the VDC can reduce the execution cycles of programs by 3.7%~ 21.5% with only additional 7.3% and 6.3% chip area and power cost, compared with the pure single-port VM scheme.