Title :
A power-on reset pulse generator for low voltage applications
Author :
Yasuda, Takeo ; Yamamoto, Masaaki ; Nishi, Takafumi
Abstract :
A power-on reset pulse generation (POR-PG) circuit for low voltage application is proposed. This circuit improves pulse height and noise immunity compared with prior circuits considering process, temperature, and voltage variations. The circuit is implemented in small area in the input/output buffer area of an integrated LSI of a microprocessor and a hard-disk controller for the internal power supply voltage of 2.5 V and 1.8 V with 0.25-μm CMOS technology. According to the simulation, by tuning the "Charge Clamp" circuit, this POR-PG in 0.18-μm, 1.35-V V dd-target CMOS technology also operates correctly
Keywords :
CMOS integrated circuits; buffer circuits; large scale integration; low-power electronics; microprocessor chips; pulse generators; 0.25 micron; 1.8 V; 2.5 V; CMOS technology; LSI; charge clamp; hard disk controller; input/output buffer; low-voltage circuit; microprocessor; noise immunity; power-on reset pulse generator; pulse height; CMOS technology; Integrated circuit technology; Large scale integration; Low voltage; Microprocessors; Pulse circuits; Pulse generation; Pulsed power supplies; Temperature; Voltage control;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922308
