Early zero detection [integrated adder/subtracter/zero-detector]

We present an integrated adder/subtracter/zero-detector in which the zero detection completes well before the sum or difference is known. Previous zero detectors either required the sum to be available before they could complete, or were not well integrated with the ALU. We avoid these problems by exploiting the properties of half-adder form. Sums in half-adder form can be computed very quickly (with the delay of a half adder), yet they have enough structure so that many of the properties of the final sum can be easily detected. Our zero detector is faster than any previously described, requires only a small amount of additional circuitry in the ALU, and adds little or nothing to the overall delay of the ALU. We also examine some of the architectural implications of early zero detection: faster branching, more instruction-level parallelism, more powerful instructions, and reduced hardware needs for supporting speculative execution