A Scan-Based Delay Test Method for Reduction of Overtesting

This paper presents a scan-based delay test method, called sequential-broad-side (SeBoS), to minimize overtesting of delay test. We consider two critical reasons for overtesting which are the existence of illegal states in sequential circuits and the high IR drop caused by power dissipation during structural test. The proposed SeBoS method inserts several slow clock cycles before applying the fast clock for detecting delay faults, thus considerable illegal states can be avoided and IR drop can be reduced. Illegal states are not necessarily computed before test generation. They can be accumulated and expanded during the automatic test pattern generation (ATPG) process. The derived illegal states are then used to guide test generation for the remaining faults. Compared with previous methods, the SeBoS method can avoid more illegal states when considering the same number of time frames. Experimental results on ISCAS-89 benchmark circuits show the effectiveness of the method.