DocumentCode
3091671
Title
A Processor-DMA-Based Memory Copy Hardware Accelerator
Author
Su, Wen ; Wang, Ling ; Su, Menghao ; Liu, Su
fYear
2011
fDate
28-30 July 2011
Firstpage
225
Lastpage
229
Abstract
For many Operating Systems and device drivers, memory copy is the most time-consuming operation which has always been paid special attention. In this paper, we propose a processor DMA based memory copy hardware accelerator with the goal to reduce the instructions executed on CPU, and exploit the parallelism between computing and data transfer in memory copy. This is accomplished by taking advantage of a proposed Direct Memory Access (DMA) engine in the processor which overcomes many conventional DMA engine shortcomings. Experimental results show that the proposed hardware solution achieves a speedup of 14.79 compared with the optimized software solution and an overlap of 81.8% in computing and data transfer on average.
Keywords
file organisation; memory architecture; storage management chips; CPU; data transfer; device drivers; direct memory access engine; instruction reduction; operating systems; processor-DMA-based memory copy hardware accelerator; Acceleration; Bandwidth; Central Processing Unit; Computer architecture; Engines; Hardware; Software; DMA; accelerator; memory copy; processor;
fLanguage
English
Publisher
ieee
Conference_Titel
Networking, Architecture and Storage (NAS), 2011 6th IEEE International Conference on
Conference_Location
Dalian, Liaoning
Print_ISBN
978-1-4577-1172-5
Electronic_ISBN
978-0-7695-4509-7
Type
conf
DOI
10.1109/NAS.2011.15
Filename
6005465
Link To Document