• DocumentCode
    3091686
  • Title

    Oscillatorless clock multiplication

  • Author

    Aguiar, Rui L. ; Santos, Diizis M.

  • Author_Institution
    Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
  • Volume
    4
  • fYear
    2001
  • fDate
    6-9 May 2001
  • Firstpage
    630
  • Abstract
    This paper presents a technique for clock multiplication without local oscillators. This technique uses a DLL, thus presenting lower jitter than traditional PLL-based oscillator systems. Furthermore, it provides directly 50% duty-cycle clocks. This method is implemented both in a programmable custom circuit able to perform clock multiplication with integer factors from 2 to 8, and in a simpler hybrid system. Both simulations in the full-custom design and experimental results in the hybrid system support our proposal
  • Keywords
    clocks; delay lock loops; frequency multipliers; timing jitter; DLL; directly 50% duty-cycle clocks; integer factors; jitter; oscillatorless clock multiplication; programmable custom circuit; Circuit simulation; Clocks; Delay; Frequency conversion; Frequency synchronization; Integrated circuit interconnections; Jitter; Local oscillators; Phase locked loops; Telecommunications;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
  • Conference_Location
    Sydney, NSW
  • Print_ISBN
    0-7803-6685-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2001.922316
  • Filename
    922316