A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding

The partitioning resources like pipelines and register files among clusters is proved to be an effective way to improve performance and scalability. However, improvement in scalability is limited by traditional instruction encoding schemes that quickly run out of bits in fixed-length instruction words to encode multiple register operands. Meanwhile, clustered processors may come at a cost of performance degradation, the major cause of which is the limited data locality arising from the lack of available registers and functional units. This paper introduces a highly scalable clustered architecture (HiSCA) to improve the scalability and performance of clustered processors. The pipeline of HiSCA provides high performance through in-order issuing, out-of-order execution and parallel but in-order commitment, while releasing instruction issuing from the heavy burden of dynamic scheduling. The hardware/software instruction encoding scheme of HiSCA splits instruction stream into chains of instructions (packs), and provides common information of instructions in the same packs in dedicated instruction words, thus reducing the total amount of information encoded in the instructions within the packs. HiSCA scales efficiently to 32 clusters with 1024 general purpose registers. Experiment results show that, for a 4-cluster and 8-issue configuration, HiSCA can achieve a 4.6% improvement in frequency with minimal hardware overhead, and an average of 13.3% performance speedup at the cost of 1.9% overhead to code size, compared with a traditional clustered processor with nearly the same hardware complexity.