DocumentCode
3091769
Title
A new algorithm for division in hardware
Author
Kantabutra, Vitit
Author_Institution
Dept. of Math., Idaho State Univ., Pocatello, ID, USA
fYear
1996
fDate
7-9 Oct 1996
Firstpage
551
Lastpage
556
Abstract
This paper presents a new algorithm for fast hardware division, where two or three dividend bits are retired per iteration. The advantage that this algorithm has over radix-4 SRT is that it is much simpler requiring no lookup table and requiring the comparison of only one two-bit operand pair per iteration. Due to its simplicity, the new algorithm is much easier to implement and verify than radix-4 SRT and is quite likely to be faster as well
Keywords
digital arithmetic; digital arithmetic; dividend bits; fast hardware division; radix-4 SRT; Algorithm design and analysis; Circuit testing; Computer science; Costs; Hardware; Logic gates; Mathematics; Programmable logic arrays; Read only memory; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-7554-3
Type
conf
DOI
10.1109/ICCD.1996.563606
Filename
563606
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