Title :
A new algorithm for division in hardware
Author :
Kantabutra, Vitit
Author_Institution :
Dept. of Math., Idaho State Univ., Pocatello, ID, USA
Abstract :
This paper presents a new algorithm for fast hardware division, where two or three dividend bits are retired per iteration. The advantage that this algorithm has over radix-4 SRT is that it is much simpler requiring no lookup table and requiring the comparison of only one two-bit operand pair per iteration. Due to its simplicity, the new algorithm is much easier to implement and verify than radix-4 SRT and is quite likely to be faster as well
Keywords :
digital arithmetic; digital arithmetic; dividend bits; fast hardware division; radix-4 SRT; Algorithm design and analysis; Circuit testing; Computer science; Costs; Hardware; Logic gates; Mathematics; Programmable logic arrays; Read only memory; Table lookup;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1996. ICCD '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-7554-3
DOI :
10.1109/ICCD.1996.563606
