An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling

Soft errors, a concern for space applications in the past, became a critical issue in deep sub-micron VLSI design for the continuous technology scaling. An automated fault injection technique is employed to characterise the recovery coverage and soft error sensitivity of the VHDL based design. Lexical and syntax analysis technique is developed to perform automated fault injection task. Stratified sampling technique is used to reduce the fault injection overheads. A fault injector, HSECT (HIT soft error characterization toolkit) is developed and 3,000 soft errors are injected into a simple RISC processor, DP32-processor. The recovery coverage and soft error sensitivity of the processor are also further investigated to direct the future design of the fault- tolerant and dependable circuit.