Scalability of scheduled data flow architecture (SDF) with register contexts

Our new architecture called scheduled data flow (SDF) system deviates from current trend of building complex hardware to exploit instruction level parallelism (ILP) by exploring a simpler, yet powerful execution paradigm that is based on data flow, multi-threading and decoupling of memory accesses from execution. A program is partitioned into non-blocking threads. In addition, all memory accesses are decoupled from the thread´s execution. Data is pre-loaded into the thread´s context (registers), and all results are post-stored after the completion of the thread´s execution. Even though multi-threading and decoupling are possible with control-flow architecture, the non-blocking and functional nature of the SDF system make it easier to coordinate the memory accesses and execution of a thread. In this paper we show some recent improvements on SDF implementation, whereby threads exchange data directly in register contexts, thus eliminating the need for creating thread frames. Thus it is now possible to explore the scalability of our architecture´s performance when more register contexts are included on the chip.