DocumentCode :
309239
Title :
Cellular automata for generating deterministic test sequences
Author :
Kagaris, Dimitrios ; Tragoudas, Spyros
Author_Institution :
Southern Illinois Univ., Carbondale, IL, USA
fYear :
1997
fDate :
17-20 Mar 1997
Firstpage :
77
Lastpage :
81
Abstract :
We propose an on-chip test pattern generator that uses a one-dimensional cellular automaton (CA) to generate either a precomputed sequence of test patterns or pairs of test patterns for path delay faults. To our knowledge, this is the first approach that guarantees successful on-chip generation of a given test pattern sequence (or a given test set for path delay faults) using a finite number of CA cells. Given a pair of columns (Cu,Cv) of the test matrix, the proposed method uses alternative “linking procedures” Pj that compute the number of extra CA cells to enable the generation of (Cu,Cv) by the CA. A systematic approach uses the linking procedures to minimize the total number of needed CA cells. Experimental results show that the hardware overhead is often reasonable. The performance of the scheme depends on an appropriate choice of linking procedures Pj
Keywords :
automatic testing; built-in self test; cellular automata; integrated circuit testing; logic testing; sequences; BIST; cellular automata; deterministic test sequences; onchip test pattern generator; one-dimensional cellular automaton; path delay faults; Automatic test pattern generation; Automatic testing; Built-in self-test; Computer science; Delay; Greedy algorithms; Hardware; Joining processes; Multiplexing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7786-4
Type :
conf
DOI :
10.1109/EDTC.1997.582336
Filename :
582336
Link To Document :
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