Cellular automata for generating deterministic test sequences

We propose an on-chip test pattern generator that uses a one-dimensional cellular automaton (CA) to generate either a precomputed sequence of test patterns or pairs of test patterns for path delay faults. To our knowledge, this is the first approach that guarantees successful on-chip generation of a given test pattern sequence (or a given test set for path delay faults) using a finite number of CA cells. Given a pair of columns (C_u,C_v) of the test matrix, the proposed method uses alternative “linking procedures” P_j that compute the number of extra CA cells to enable the generation of (C_u,C_v) by the CA. A systematic approach uses the linking procedures to minimize the total number of needed CA cells. Experimental results show that the hardware overhead is often reasonable. The performance of the scheme depends on an appropriate choice of linking procedures P_j