Uniform Random Number Generator Using Leap Ahead LFSR Architecture

Uniform Random Number Generator (URNG) is a key element in most applications which run on FPGA based hardware accelerators. As multi-bits is required and a normal LFSR could only generate one bit per cycle, more than one LFSR is needed in a URNG. In this paper, we introduce a new kind of URNG using Leap-Ahead LFSR Architecture which could generate an m-bits random number per cycle using only one LFSR. We analyze its architecture, present the expression of the period and point out how to choose the taps of the LFSR. Finally, a 18-bits URNG is implemented on Xilinx Vertex IV FPGA. By comparison, the Leap-Ahead LFSR Architecture URNG consumes less than 40 slices which is only 10% of what the Multi-LFSRs architecture consumes and acquires very good Area Time performance and Throughput performance that are 2.18×10-9 slices×sec per bit and 17.87×109 bits per sec.