• DocumentCode
    3092646
  • Title

    Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect

  • Author

    Bouchakour, R. ; Harabech, N. ; Canet, P. ; Boivin, Ph. ; Mirabel, J.M.

  • Author_Institution
    L2MP-UMR, CNRS, Marseille, France
  • Volume
    4
  • fYear
    2001
  • fDate
    6-9 May 2001
  • Firstpage
    822
  • Abstract
    A model for static and transient simulations of an electrically erasable programmable read only memory cell has been developed. This physical compact model is based on charge sheet approach which is able to describe the complete electrical behavior of the cell. In this model, we have introduced the dependence of the tunneling capacitance as a function of the voltage across the tunnel oxide and the floating gate depletion effect. This model has been successfully implemented in common circuit simulators and used for the study of the write/erase operations in a memory cell. The simulations compared to the experimental results are in good agreement
  • Keywords
    EPROM; capacitance; circuit simulation; integrated circuit modelling; tunnelling; charge sheet model; circuit simulation; floating gate EEPROM cell; polysilicon gate depletion; tunneling capacitance; Capacitance; Circuit simulation; EPROM; Electron traps; Equivalent circuits; Nonvolatile memory; Polarization; Threshold voltage; Tunneling; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
  • Conference_Location
    Sydney, NSW
  • Print_ISBN
    0-7803-6685-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2001.922364
  • Filename
    922364