Title :
A digital Class D amplifier design embodying a novel sampling process and pulse generator
Author :
Li, Huiyum ; Gwee, Bah Hwee ; Chang, Joseph S.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
Abstract :
A digital Class D amplifier comprises a digital Pulse Width Modulation (PWM) and an output stage (and low pass filter). Digital PWM involves two steps, the sampling process and the pulse generation. In this paper, we propose a digital Class D amplifier based on our sampling process and a novel PWM pulse generator design. The pulse generator is based on the combination of the fast clock counter and the tapped delay line based techniques. Our proposed Class D amplifier features a simple circuit implementation (small IC area), low power operation (expected ~90 μW@1.1 V, fsampling=16 kHz based on a 0.25 μm CMOS process) and a highly desirable low harmonic distortion (expected <0.7%)
Keywords :
CMOS digital integrated circuits; audio-frequency amplifiers; harmonic distortion; low-power electronics; pulse generators; pulse width modulation; 0.25 micron; 1.1 V; 16 kHz; 90 muW; CMOS circuit; audio amplifier; clock counter; digital class D amplifier; digital pulse width modulation; harmonic distortion; low-pass filter; low-power design; pulse generator; sampling process; tapped delay line; Clocks; Counting circuits; Delay lines; Digital modulation; Low pass filters; Pulse amplifiers; Pulse generation; Pulse width modulation; Sampling methods; Space vector pulse width modulation;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922365
