DocumentCode :
309266
Title :
Accurate timing model for the CMOS inverter
Author :
Bisdounis, L. ; Nikolaidis, S. ; Koufopavlou, O. ; Goutis, C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Patras Univ., Greece
Volume :
1
fYear :
1996
fDate :
13-16 Oct 1996
Firstpage :
89
Abstract :
This paper introduces an accurate, analytical timing model for the CMOS inverter. Analytical output waveform expressions for all the inverter operation regions and input waveform slopes are derived, which take into account the complete expression of the short-circuit current and the gate-to-drain coupling capacitance
Keywords :
CMOS digital integrated circuits; delays; integrated circuit modelling; logic gates; timing; waveform analysis; CMOS inverter; analytical output waveform expressions; analytical timing model; gate-to-drain coupling capacitance; input waveform slopes; inverter operation regions; propagation delay; short-circuit current; Capacitance; Coupling circuits; Differential equations; Inverters; MOS devices; Physics computing; Propagation delay; Semiconductor device modeling; Threshold voltage; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
Conference_Location :
Rodos
Print_ISBN :
0-7803-3650-X
Type :
conf
DOI :
10.1109/ICECS.1996.582696
Filename :
582696
Link To Document :
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