Low-power design of array architectures

Author

Soudris, D. ; Theodoridis, G. ; Theoharis, S. ; Thanailakis, A.

Author_Institution

Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece

Volume

1

fYear

1996

fDate

13-16 Oct 1996

Firstpage

120

Abstract

A systematic methodology for designing array architectures taking into consideration the criterion of the power dissipation, is introduced. We start from the algorithm representation and end at the array processor level. Using optimal linear transformations at the algorithmic level, many array architectures in terms of the hardware complexity, the power dissipation, the latency, and the throughput rate can be derived. The proposed methodology can be applied in many well-known DSP algorithms

Keywords

VLSI; array signal processing; digital signal processing chips; integrated circuit design; parallel architectures; pipeline processing; DSP algorithms; VLSI; algorithm representation; array processor architectures; hardware complexity; latency; optimal linear transformations; pipelineability; power dissipation; throughput rate; Computer architecture; Delay; Design methodology; Digital signal processing; Digital signal processing chips; Hardware; Iterative algorithms; Power dissipation; Signal processing algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.582713

Filename

582713