Highly efficient 24-GHz CMOS linear power amplifier with an adaptive bias circuit

Author

Hyunji Koo ; Bonhoon Koo ; Songcheol Hong

Author_Institution

Dept. of Electr. Eng., KAIST, Daejeon, South Korea

fYear

2012

fDate

4-7 Dec. 2012

Firstpage

7

Lastpage

9

Abstract

A 24 GHz Power amplifier (PA) with high efficiency designed in the 0.13-μm CMOS process is presented. The proposed adaptive-bias circuit is used to improve the efficiency. The quiescent power consumption is 79.2 mW, which is improved by 53.8mW, compared to that of the optimized fixed-biased (0.6V) PA. Power added efficiency (PAE) and output power (P_OUT) at a 1-dB-gain-compression-power (P_1dB) is 15.6 % and 13.3 dBm, respectively. This result is improved as much as 4% and 1.2dB, compare to that of PA with fixed-bias of 0.6V.

Keywords

CMOS analogue integrated circuits; microwave power amplifiers; CMOS linear power amplifier; CMOS process; adaptive bias circuit; adaptive-bias circuit; frequency 24 GHz; gain 1 dB; output power; power 79.2 mW; power added efficiency; quiescent power consumption; size 0.13 mum; CMOS integrated circuits; CMOS process; Gain; Logic gates; Power amplifiers; Power generation; Semiconductor device measurement; 24GHz; CMOS; adaptive bias; k-band; power amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference Proceedings (APMC), 2012 Asia-Pacific

Conference_Location

Kaohsiung

Print_ISBN

978-1-4577-1330-9

Electronic_ISBN

978-1-4577-1331-6

Type

conf

DOI

10.1109/APMC.2012.6421480

Filename

6421480