Design of low-power baseband-processor for RFID tag

Author

Yan, He ; Jianyun, Hu ; Qiang, Li ; Hao, Min

Author_Institution

Auto-ID Lab., Fudan Univ., Shanghai

fYear

2006

fDate

23-27 Jan. 2006

Lastpage

63

Abstract

This paper analyzes the power consumption of an RFID tag and presents a new architecture of a low-power baseband-processor for this special passive tag. The tag consists of a power reception system, an emitter/receiver analog module, an EEPROM and a low-power baseband-processor, compatible with the newest EPCtrade C1G2 UHF RFID protocol. Meanwhile some novel and advanced low-power technologies are adopted for the special low-power baseband-processor, which not only implements the anti-collision schemes and authorization scheme, but also executes read/write operation to EEPROM. The chip was designed and fabricated using 0.35 mum 3 metal layers CMOS technology successfully

Keywords

CMOS integrated circuits; EPROM; integrated circuit design; low-power electronics; radiofrequency identification; receivers; 0.35 micron; CMOS; EEPROM; EPC C1G2 UHF RFID protocol; RFID tag; emitter-receiver analog module; low-power baseband-processor design; power consumption; power reception system; CMOS technology; EPROM; Energy consumption; Equations; Power dissipation; RFID tags; Radio frequency; Radiofrequency identification; Technical Activities Guide -TAG; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Applications and the Internet Workshops, 2006. SAINT Workshops 2006. International Symposium on

Conference_Location

Phoenix, AZ

Print_ISBN

0-7695-2510-5

Type

conf

DOI

10.1109/SAINT-W.2006.15

Filename

1581370