Title :
A 1V 18 dBm 60GHz power amplifier with 24dB gain in 65nm LP CMOS
Author :
Linhui Chen ; Lianming Li ; Tie Jun Cui
Author_Institution :
Sch. of Inf. Sci. & Eng., Southeast Univ., Nanjing, China
Abstract :
A 60 GHz 4-way power-combining power amplifier (PA) is realized in a 65nm LP CMOS. The PA consists of three common-source (CS) pseudo-differential stages, in which a capacitive neutralization is used to increase the reverse isolation and the maximum gain (Gmax). To achieve high gain within a small area, a new inter-stage impedance matching network is proposed, consisting of transformer, transmission line and shunt inductor. The PA exhibits a small-signal gain of about 24dB, with 3dB bandwidth of more than 10GHz. The saturated output power (Psat) is 18 dBm and 19 dBm with 1 V and 1.2 V supply voltage, respectively. The peak PA E is 13.2% and P1dB is 14.8 dBm. The PA occupies an area of 0.74mm2, including pads.
Keywords :
CMOS analogue integrated circuits; MMIC power amplifiers; field effect MIMIC; impedance matching; inductors; millimetre wave power amplifiers; transformers; transmission lines; 4-way power-combining power amplifier; LP CMOS; capacitive neutralization; common-source pseudodifferential stages; frequency 60 GHz; gain 24 dB; inter-stage impedance matching network; maximum gain; reverse isolation; shunt inductor; size 65 nm; transformer; transmission line; voltage 1 V; voltage 1.2 V; CMOS integrated circuits; Circuit stability; Inductors; Power amplifiers; Power generation; Power system stability; Shunts (electrical); capacitive neutralization; millimeter wave; power amplifier; power combining; transformer;
Conference_Titel :
Microwave Conference Proceedings (APMC), 2012 Asia-Pacific
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4577-1330-9
Electronic_ISBN :
978-1-4577-1331-6
DOI :
10.1109/APMC.2012.6421482
