A hardware/software codesign partitioner for ASIP design

This paper introduces a new codesign partitioning method used in automating the design of ASIP (Application Specific Integrated Processor). The codesign partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software such that a certain performance goal is met using minimum hardware resources. A branch-and-bound algorithm is used to solve the presented formalization. The proposed method is found to be effective in producing a quality design in reasonable time with a minimum of design interaction