DocumentCode :
3092957
Title :
An inductorless peaking technique applied to MOS current-mode logic gates
Author :
Badel, S. ; Leblebici, Yusuf
Author_Institution :
Microelectronic Systems Laboratory, Swiss Federal Institute of Technology (EPFL), CH-1015 Lausanne, Switzerland
fYear :
2004
fDate :
8-9 Nov. 2004
Firstpage :
36
Lastpage :
39
Abstract :
A novel inductorless peaking technique is demonstrated to improve the time-domain response of MOS current mode logic (MCML) gates. The proposed circuit design occupies signi-cantly less area compared to passive inductive peaking solutions, and achieves a speed increase of up to 17% in detailed post-layout simulations, and up to 8.5% in experimental validation. Sample circuits designed using a standard 0.18 μm CMOS technology with 1.8 V power supply exhibit propagation delay times of about 35ps, which allows reliable circuit operation at GHz range clock frequency. The circuit technique discussed here is suitable for cell-bared high-density logic designs.
Keywords :
CMOS logic circuits; Circuit simulation; Delay; Logic design; Logic gates; Noise reduction; Noise robustness; Power dissipation; Switching circuits; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Norchip Conference, 2004. Proceedings
Conference_Location :
Oslo, Norway
Print_ISBN :
0-7803-8510-1
Type :
conf
DOI :
10.1109/NORCHP.2004.1423816
Filename :
1423816
Link To Document :
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