Title :
An efficient 2-D DWT architecture via resource cycling
Author :
Lin, Tay-Jyi ; Jen, Chein-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Most DWT architectures reuse the filterbank modules for all decomposition levels to improve the hardware utilization but they should be implemented for the worst-case storage and computational precision requirements. We propose a novel reconfigurable 2-D DWT architecture in this paper that dynamically recycles the unused storage for computation resources with increasing precision as the decomposition level goes higher. We have implemented and verified this cost-effective architecture with PDA (Parallel Distributed Arithmetic) filterbank modules on the Xilinx XCV300-PQ230-6 FPGA and shown great improvement on PSNR/area ratio
Keywords :
VLSI; channel bank filters; digital signal processing chips; discrete wavelet transforms; distributed arithmetic; parallel architectures; reconfigurable architectures; 2D DWT architecture; PDA; PSNR/area ratio; Xilinx XCV300-PQ230-6 FPGA; computation resources; decomposition level; parallel distributed arithmetic; reconfigurable architecture; resource cycling; Arithmetic; Computer architecture; Convolution; Discrete wavelet transforms; Field programmable gate arrays; Filter bank; Fourier transforms; Hardware; Processor scheduling; Wavelet coefficients;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922387
