• DocumentCode
    3093104
  • Title

    Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution

  • Author

    Chuang, Chun-Yu ; Mak, Wai-Kei

  • Author_Institution
    Ind. Technol. Res. Inst.
  • fYear
    2009
  • fDate
    16-18 March 2009
  • Firstpage
    68
  • Lastpage
    73
  • Abstract
    Statistical static timing analysis (SSTA) is indispensable for nanometer manufacturing under process variability. The process variations cause significant uncertainty in VLSI circuit timing and this makes yield control and timing verification a very difficult challenge. SSTA is suitable for timing estimation and design for manufacturability under process variation. However, most of the existing SSTA techniques have difficulty in keeping closed-form expressions after max operations and sum operations on variation sources. For computing a converged statistical form after max operations and sum operations, we propose an analytical approach which innovates the concept given by first-order canonical form and skew-normal distribution to solve this problem. These derived results are in closedform and precise when timing sources have the skew-normal distribution or normal distribution. Experimental results show that, compared to the Monte-Carlo simulation, our approach estimates the timing constraint and predicts the yield within 1.5% and 0.2% error, respectively.
  • Keywords
    Monte Carlo methods; VLSI; design for manufacture; integrated circuit design; integrated circuit manufacture; statistical analysis; Monte-Carlo simulation; VLSI circuit; closed-form parameterized block; first-order canonical form; nanometer manufacturing; process variation; skew-normal distribution; statistical static timing analysis; Algorithm design and analysis; Circuits; Computer industry; Computer science; Information analysis; Manufacturing industries; Manufacturing processes; Planarization; Timing; Very large scale integration; Physical Design; SSTA; Statistical Static Timing Analysis; Timing Analysis; VLSI;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-2952-3
  • Electronic_ISBN
    978-1-4244-2953-0
  • Type

    conf

  • DOI
    10.1109/ISQED.2009.4810271
  • Filename
    4810271