Architecture design exploration of three-dimensional (3D) integrated DRAM

Motivated by increasingly promising three-dimensional (3D) integration technologies, this paper reports an architecture design of 3D integrated dynamic RAM (DRAM). To accommodate the potentially significant pitch mismatch between DRAM word-line/bit-line and through silicon vias (TSVs) for 3D integration, this paper presents two modestly different coarse-grained inter-sub-array 3D DRAM architecture partitioning strategies. Furthermore, to mitigate the potential yield loss induced by 3D integration, we propose an interdie inter-sub-array redundancy repair approach to improve the memory repair success rate. For the purpose of evaluation, we modified CACTI 5 to support the proposed coarse-grained 3D partitioning strategies. Estimation results show that, for the realization of a 1 Gb DRAM with 8 banks and 256-bit data I/O, such 3D DRAM design strategies can effectively reduce the silicon area, access latency, and energy consumption compared with 3D packaging with wire bonding and conventional 2D design. We further developed a memory redundancy repair simulator to demonstrate the effectiveness of proposed inter-die inter-subarray redundancy repair approach.