DocumentCode :
3093314
Title :
Revisiting the linear programming framework for leakage power vs. performance optimization
Author :
Jeong, Kwangok ; Kahng, Andrew B. ; Yao, Hailong
Author_Institution :
ECE Dept., Univ. of California at San Diego, San Diego, CA
fYear :
2009
fDate :
16-18 March 2009
Firstpage :
127
Lastpage :
134
Abstract :
This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgate-biasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we pre-process timing libraries to estimate the linear relation - in every slew-load condition - between the gate delay and gate length by linear fitting; we then optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multi-Lgate and Lgate-biasing knobs. We also show a promising application to circuit timing legalization, a problem which frequently arises when implementation and sign off timers differ. Overall, our results show strong viability of LP based estimation and optimization: compared with the commercial tools, we: (1) shift the achievable delay-leakage tradeoff curve in a positive way, and (2) more accurately maintain prescribed timing constraints.
Keywords :
delays; linear programming; minimisation; 65GP industry testbed; circuit performance; circuit timing legalization; delay-leakage tradeoff curve; gate delay; gate length; leakage power; linear programming framework; multiLgate footprint-compatible libraries; multiple knobs; performance optimization; positive timing slack minimization; post-layout Lgate-biasing; slew-load condition; timing constraints; total leakage power; Circuit optimization; Circuit testing; Degradation; Delay estimation; Energy consumption; Fitting; Industrial relations; Libraries; Linear programming; Timing; Leakage power; Lgate-biasing; linear programming; multi-Lgate; timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
Type :
conf
DOI :
10.1109/ISQED.2009.4810282
Filename :
4810282
Link To Document :
بازگشت