DocumentCode :
3093495
Title :
Sequential equivalence checking
Author :
Mathur, A. ; Fujita, M. ; Balakrishnan, M. ; Mitra, R.
Author_Institution :
Calypto Design Syst., Santa Clara, CA, USA
fYear :
2006
fDate :
3-7 Jan. 2006
Abstract :
Summary form only for tutorial. We define sequential equivalence checking (SEC) to be the process of checking functional equivalence between models that do not satisfy the assumption of one-to-one flop mapping. The need for SEC is being driven by the widespread use of system-level modeling in SystemC/C/C++ for developing golden functional reference models, models for micro-architectural refinement and platforms for software development. This tutorial identifies the design flows where SEC can be effectively used, identify the key technologies needed for developing an effective SEC tool and demonstrate its value proposition in design flows.
Keywords :
circuit CAD; formal verification; high level synthesis; integrated circuit design; functional equivalence; functional reference models; microarchitectural refinement; one-to-one flop mapping; sequential equivalence checking; software development; system-level modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
Conference_Location :
Hyderabad, India
ISSN :
1063-9667
Print_ISBN :
0-7695-2502-4
Type :
conf
DOI :
10.1109/VLSID.2006.145
Filename :
1581418
Link To Document :
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