DocumentCode :
3093515
Title :
Erect of regularity-enhanced layout on printability and circuit performance of standard cells
Author :
Sunagawa, Hiroki ; Terada, Haruhiko ; Tsuchiya, Akira ; Kobayashi, Kazutoshi ; Onodera, Hidetoshi
Author_Institution :
Dept. of Commun. & Comput. Eng., Kyoto Univ., Kyoto
fYear :
2009
fDate :
16-18 March 2009
Firstpage :
195
Lastpage :
200
Abstract :
As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-or among manufacturability, cost, and performance for each process technology. This paper discusses the erect of layout regularity on printability and circuit performance in 90-45 nm processes by lithography simulation and real chip measurement. It is shown that we can focus more on circuit performance with less on layout regularity in a 90 nm process while adequate amount of regularity is imperative for ensuring proper amount of lithographic process windows in a 45 nm process. We demonstrate the quantitative evaluation of the trade-or between printability and circuit performance of regularity-enhanced standard cells.
Keywords :
NAND circuits; circuit layout; photolithography; semiconductor process modelling; circuit performance; optical proximity correction; photo lithography; printability; real chip measurement; regularity-enhanced layout; restricted design rule; transistor; two-input NAND; Appropriate technology; Circuit optimization; Circuit simulation; Communication standards; Costs; Lithography; Maintenance engineering; Manufacturing processes; Ring oscillators; Semiconductor device measurement; DFM; Layout Regularity; Performance; Standard Cell; Variability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
Type :
conf
DOI :
10.1109/ISQED.2009.4810293
Filename :
4810293
Link To Document :
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