DocumentCode
3093607
Title
Estimation and optimization of reliability of noisy digital circuits
Author
Sivaswamy, Satish ; Bazargan, Kia ; Riedel, Marc
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN
fYear
2009
fDate
16-18 March 2009
Firstpage
213
Lastpage
219
Abstract
With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efficient techniques for analyzing and optimizing circuits for reliability. To address this problem, we propose an exact analysis method based on circuit transformations. Also, we propose a hybrid method that combines exact analysis with probabilistic measures to estimate reliability. We use such measures in a rewiring-based optimization framework to optimize reliability. Our hybrid approach offers a speedup of 56X when compared to a pure Monte Carlo simulation-based approach with only a 3.5% loss in accuracy. Our optimization framework improves reliability by about 10% accompanied by a 6.9% reduction in circuit area.
Keywords
circuit noise; circuit reliability; digital circuits; network synthesis; optimisation; circuit transformations; circuits reliability; digital circuit designers; noisy digital circuits; reliability optimization; rewiring-based optimization; Circuit analysis; Circuit analysis computing; Circuit faults; Circuit noise; Circuit simulation; Circuit synthesis; Design optimization; Digital circuits; Monte Carlo methods; Signal synthesis; Automatic Synthesis; Fault-Tolerance; Optimization; Reliability; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-2952-3
Electronic_ISBN
978-1-4244-2953-0
Type
conf
DOI
10.1109/ISQED.2009.4810296
Filename
4810296
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