Combinational logic SER estimation with the presence of re-convergence

As transistor feature size scales down, re-convergence takes more and more significant effect to SER (soft error rate) estimation in combinational logic. In this paper, we propose 4 forms of re-convergence in 2-input logic gates, ROR, RSUB, RAND and RXOR, and for each form the sensitization condition is presented. The results are extended to more complex gates. Based on our re-convergence analysis technique, we implement a SER analyze framework of combinational logic with re-convergence, SERAR (soft error rate analyze with re-convergence). Experiments on ISCAS´85 benchmark circuit show that re-convergence introduces average 12% ~ 41% error in SER estimation for each gate.