High-speed on-chip interconnect modeling for circuit simulation

We investigate the relevance of inductance in interconnect models through simulation of an on-chip bus described by a HSPICE W-element, a RLC-network, and a RC-network, respectively. For worst-case delay estimations, we show that the simplest RC-model h sufficient. We further demonstrate the importance of including inductance in noise and edge-rate simulations. For the longest interconnect investigated, the W-element and RC-network differ by 20.6% in overshoot, 156% in ground noise, 53.2% in crosstalk and 61.7% in edge-rule simulations. The W-element and RLC-network never diverge by more than 2% in overshoot, 12.4% in ground noise, 8.9% in crosstalk and 5.6% in edge-rate simulations.