DocumentCode :
3093695
Title :
Analog circuit performance issues with aggressively scaled gate oxide CMOS technologies
Author :
Narasimhulu, K. ; Rao, V. Ramgopal
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India
fYear :
2006
fDate :
3-7 Jan. 2006
Abstract :
MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage.
Keywords :
CMOS digital integrated circuits; MOSFET; analogue circuits; current mirrors; leakage currents; mixed analogue-digital integrated circuits; semiconductor device models; semiconductor process modelling; 1 to 2 nm; MOS transistors; amplifier circuits; analog circuit design; current mirror circuits; digital CMOS technologies; gate leakage; mixed signal circuits; short channel effects; Analog circuits; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS technology; Dielectrics; Gate leakage; Leakage current; MOSFETs; Mirrors; Tutorial;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2502-4
Type :
conf
DOI :
10.1109/VLSID.2006.84
Filename :
1581430
Link To Document :
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