Baseband digital predistorter with quadrature error correction

In this paper simulation and measurement results of a FPGA implementation of a baseband digital complex gain predistorter with a quadrature modulator error correction algorithm are presented. In the measurements a 40 dB three stage power ampli er chain with an analog quadrature modulator and demodulator was used as the device to be predistorted. The signal used in the measurements and simulations was a 30dBm 18 kHz DQPSK signal at 400 MHz carrier frequency. In simulations 40 dB ACP improvement was achieved and in the measurements over IO dB reduction in 3rd order nonlinearity was achieved.