A low power 1.8 V 4-bit 400-MHz flash ADC in 0.18μ digital CMOS

Author

Banik, Subhadeep ; Gangopadhyay, Daibashish ; Bhattacharyya, T.K.

Author_Institution

Dept.of Electron. & Elec. Comm. Engg., Indian Inst. of Technol., Kharagpur, India

fYear

2006

fDate

3-7 Jan. 2006

Abstract

This paper is devoted to the design and implementation of high speed, low power, low voltage flash analog-to-digital convertors (ADC). A 4-bit flash ADC, with a maximum acquisition speed of 400 MHz, is implemented in a 1.8 V analog supply voltage. The large input signal dynamic range is handled using a fast switching common mode jump circuit, implemented with complementary pass transistors, which eliminates the need for high input-common-mode-range (ICMR) preamplifier based comparators. The measured INL/DNL is 0.4/1.1 LSB. The signal-to-noise-plus-distortion ratio (SNDR) obtained at 12.5 MHz input is 21.25 dB. The spurious-free dynamic range (SFDR) is 27.6 dB and power consumption is only 30 mW. Design and simulations results are presented in dual-poly 0.18μ pure digital CMOS technology.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; 1.8 V; 12.5 MHz; 30 mW; 4 bit; 400 MHz; comparators; complementary pass transistors; digital CMOS technology; fast switching common mode jump circuit; flash analog-to-digital convertors; CMOS technology; Circuit simulation; Computational modeling; Converters; Dynamic range; Energy consumption; Low voltage; Preamplifiers; Signal processing; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-2502-4

Type

conf

DOI

10.1109/VLSID.2006.13

Filename

1581434